Some applications such as Direct Digital Synthesizer (DDS) may employ a Delay Locked Loop (DLL) based Digital to Time Converter (DTC), also known as Phase converter, for synthesizing phase-shifted reference signals. The DTC can have a delay line with identical tap delay elements that are locked using the DLL. During a digital to time conversion, the reference signal is passed through the delay line and a tap selection logic is used to select pulses of the reference signal from the outputs of the delay line. Consequently, a plurality of phase-shifted reference signals are generated through the outputs of the delay line. These phase-shifted reference signals can be combined in various ways to obtain output signals of varying frequencies.
Spectral purity of the output signals depends upon the accuracy of the phase-shifted reference signals. In a real scenario, due to finite errors associated with Integrated Chip (IC) manufacturing process, a delay mismatch may exist between the tap delay elements, rendering them non-identical. Due to the mismatch, the time spacing between the phase-shifted reference signals may be unequal. This may lead to generation of discrete spurious signals in the output signal that have a magnitude proportionate to the error in time spacing between the phase-shifted reference signals.
The presence of spurious signals can significantly affect the quality of the output signals. Further these spurious signals are not desirable in many applications such as, a local oscillator in a transceiver system, etc. The spurious signals may cause unwanted signals to appear along with the wanted signals thus degrading system performance.
Some existing state of the art, time based sampling RF system architectures are complex and statistics based and are coupled to the process technology. Other architectures are high-power requirement solutions that necessitate the use of very high speed time interval counters. Consequently, the high-power requirement solutions lead to long duration processing of a large number of time based samples. Moreover, most of the existing solutions require complex frequency domain measurements of time based reference signal synthesis.
Accordingly, it would be desirable to have an improved means of managing digital to time conversion.
Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.